1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device including a memory cell array in which replacement with a spare memory cell can be performed.
2. Description of the Background Art
In recent years, increased acceleration has progressed toward higher integration in semiconductor memory devices. Generally, a highly integrated semiconductor memory device is provided with spare memory cells and even in a case where a defect arises in part of memory cells in a fabrication stage, a defective memory cell having the defect therein is replaced with a spare memory cell to save one bit. A method with such redundancy replacement applied has generally been used, in which a product yield is improved.
Along with development on the scale of a semiconductor memory device, however, firstly an increase occurs in number of elements each including a spare memory cell, which are necessary to raise a product yield, and with such an increase, an increase also occurs in number of program elements for storing an address of a defective memory cell to be replaced with a spare memory cell. Such increases in the elements have entailed a problem of an increased chip area.
In order to perform the replacement, a necessity arises for storing an address of a defective memory cell in a non-volatile manner. As such means, used in many cases are program elements such as a fuse element. This fuse element is disconnected using a laser beam or the like means. In order to achieve not only sure disconnection but no damage to an element in the neighborhood thereof either, it is required that a fuse element has a size of some magnitude and no other element is present therearound. Therefore, a chip area becomes larger with more of program elements installed.
Besides, secondly, with an increase in number of program elements, a program time for saving a defective chip cannot be neglected, having further resulted in a problem of increase in a fabrication cost.
It is an object of the present invention to provide a semiconductor memory device with an improved saving rate for defective chips caused by defective memory cells.
The present invention is, being summarized, a semiconductor memory device which includes: first to fourth normal memory cell groups; first and second spare memory cells; a first select circuit; and a second select circuit.
The first to fourth normal memory cell groups each include a plurality of normal memory cells.
The first and second spare memory cells are each substituted for a defective memory cell among the plurality of normal memory cells.
The first select circuit holds address assignment information in a non-volatile manner. The first select circuit selects two normal memory cell groups among the first to fourth normal memory cell groups determined on the basis of the address assignment information together with the first spare memory cell in response to a first address value given as an input address. The first select circuit selects the other two normal memory cell groups among the first to fourth normal memory cell groups determined on the basis of address assignment information together with the second spare memory cell in response to a second address value given as an input address.
The second select circuit holds replacement information in a non-volatile manner. The second select circuit selects the first spare memory cell on the basis of the replacement information instead of a first defective memory cell among normal memory cells selected according to the first address value. The second select circuit selects the second spare memory cell on the basis of the replacement information instead of a second defective memory cell among normal memory cells selected according to the second address value.
Accordingly, a main advantage of the present invention is that a saving rate for defective chips with spare memory cells can be improved while suppressing an increase in number of spare memory cells.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.